IJCCE 2012 Vol.1(3): 179-182 ISSN: 2010-3743
DOI: 10.7763/IJCCE.2012.V1.47
DOI: 10.7763/IJCCE.2012.V1.47
Architecture and Design of High Speed Data Acquisition System
Cao Bin , Chong Ming Ying, Kyaw Swa Maung, Lai Yoon Fei, Manoj Kumar Dey, and Sandeep Dattaprasad
Abstract—Data acquisition systems are of interest for purposes such as parametric measurement and verification of data integrity, particularly for high speed memory devices such as DDR. This paper analyzes and proposes a simple principle and structure for designing one such hardware system with use of Field Programmable Gate Arrays (FPGAs). A hardware system employing this architecture is illustrated here using E2V's Analog to Digital Converters (ADC), Altera’s Stratix III and Cyclone II FPGAs and Samsung's 1Gb DDR3 memory devices for data storage.
Index Terms—Data acquisition, high speed, field programmable gate array, ADC, DDR.
Chong Ming Ying, Kyaw Swa Maung, Lai Yoon Fei, Manoj Kumar Dey, and Sandeep Dattaprasad are with Seagate Techonology, EAO, Advanced Development Engineering, 7000, Ang Mo Kio Ave 5, Singapore 569877(e-mail: sandeep.dattaprasad@gmail.com).
Cao Bin is with Institute for Infocomm Research, Embedded Systems Department, Singapore 138632
Cite: Cao Bin , Chong Ming Ying, Kyaw Swa Maung, Lai Yoon Fei, Manoj Kumar Dey, and Sandeep Dattaprasad, "Architecture and Design of High Speed Data Acquisition System," International Journal of Computer and Communication Engineering vol. 1, no. 3, pp. 179-182, 2012.
General Information
ISSN: 2010-3743 (Online)
Abbreviated Title: Int. J. Comput. Commun. Eng.
Frequency: Quarterly
DOI: 10.17706/IJCCE
Editor-in-Chief: Dr. Maode Ma
Abstracting/ Indexing: INSPEC, CNKI, Google Scholar, Crossref, EBSCO, ProQuest, and Electronic Journals Library
E-mail: ijcce@iap.org
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