Abstract—Network applications have been developed quickly during recent years, and communications between these applications involve a large quantity of data transfer through high speed networks. Deep packet inspection (DPI) becomes indispensable to ensure network application-aware security. One of the DPI services is the signature-based network intrusion detection system (NIDS), in which the implementation on software platforms has become a trend due to the advantages of high programmability and low cost. Recently, the graphic processing units (GPU) is commonly used to accelerate the packet processing because of its superior parallel processing power. Since delivering all packets to GPU causes high data transfer latency and consequently restricts the overall performance, our previous study proposed a mechanism, HPMA, to reduce the effect of transfer bottleneck and achieve higher processing speed. In this paper, we introduce an enhancement of HPMA, a capability-based hybrid CPU/GPU pattern matching algorithm (CHPMA). A preliminary experiment shows that the CHPMA not only performs as efficient as the HPMA in most cases, but also obtains higher performance gain than the HPMA under unfavorable conditions.

Index Terms—Network security, pattern matching algorithm, deep packet inspection (DPI), intrusion detection system (IDS), general-purpose graphics processing unit (GPGPU), compute unified device architecture (CUDA).

Yi-Shan Lin and Yaw-Chung Chen are with the Department of Computer Science, National Chiao Tung University, Hsinchu 30010, Taiwan.
Chun-Liang Lee is with the Department of Computer Science and Information Engineering, School of Electrical and Computer Engineering, College of Engineering, Chang Gung University, Taoyuan 33302, Taiwan.

Cite:Yi-Shan Lin, Chun-Liang Lee, Yaw-Chung Chen, "A Capability-Based Hybrid CPU/GPU Pattern Matching Algorithm for Deep Packet Inspection," International Journal of Computer and Communication Engineering vol. 5, no. 5, pp. 321-330, 2016.