Volume 3 Number 6 (Nov. 2014)
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IJCCE 2014 Vol.3(6): 442-445 ISSN: 2010-3743
DOI: 10.7763/IJCCE.2014.V3.365

Short-Term Bottleneck Detection for Process Planning in a FAB

Karam Yang, Yongho Chung, and Sang C. Park
Abstract—This paper presents a detection process for bottlenecks in a wafer FAB (fabrication) using a simulation approach. In a semiconductor manufacturing industry, a Wafer FAB facility includes various equipment and wafer products. The wafer FAB has many characteristics, such as re-entrant processing flow and batch tools. The performance of a complex manufacturing system (i. e. semiconductor wafer FAB) is mainly decided by a bottleneck. In this paper, we define the problem of a bottleneck process and propose a simulation based framework for short-term (3 shift) bottleneck detection. By the proposed framework of this paper, the performance of a wafer FAB is improved in on-time delivery and the mean of minimum of cycle time.

Index Terms—Bottleneck detection, semiconductor, simulation, wafer fab.

The authors are with the Department of Industrial Engineering, Ajou University, San 5, Woncheon-Dong, Yeongtong-Gu, Suwon 443-749, Korea (e-mail: {vision0429, scpark} @ajou.ac.kr, yongho1230@gmail.com).

Cite:Karam Yang, Yongho Chung, and Sang C. Park , "Short-Term Bottleneck Detection for Process Planning in a FAB," International Journal of Computer and Communication Engineering vol. 3, no. 6, pp. 442-445, 2014.

General Information

ISSN: 2010-3743 (Online)
Abbreviated Title: Int. J. Comput. Commun. Eng.
Frequency: Quarterly
Editor-in-Chief: Dr. Maode Ma
Abstracting/ Indexing: EI (INSPEC, IET), Google Scholar, Crossref, EBSCO, ProQuest, and Electronic Journals Library
E-mail: ijcce@iap.org
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