Abstract—This paper proposes a design method for an 8-bit multiplication with reduced delay time. Normally, two numeric data can be multiplied by repeated addition. In case of binary multiplication, combinational circuit can be designed using manual multiplication method which requires binary addition. Carry generated because of addition affects the speed of multiplication since the present addition depends on the value of previous carry. To overcome this problem, addition with the help of multiplexer is introduced and the result is an increased speed in multiplication. Even though the proposed design is mainly for FPGA implementation, it can also be implemented in ASIC as the logical delay is reduced when compared the result in Xilinx device.

Index Terms—Multiplexer, delay time, incrementer, FPGA.

G. Dhanabalan is with the Kamaraj College of Engineering and Technology, Virudhunagar, India (e-mail: dhanabalang@yahoo.com).
S. Tamil Selvi is with National Engineering College, Kovilpatti, India (e-mail: tamilgopal2004@yahoo.co.in).

Cite:Dhanabalan and Tamil Selvi, "FPGA Implementation of 8-bit Multiplier with Reduced Delay Time," International Journal of Computer and Communication Engineering vol. 2, no. 6, pp. 665-668, 2013.