Abstract—In modern VLSI technology the speed and power would always be a trade off. In contrast to that the proposed design gives better technique in improving the speed of computation with high accuracy when compared with conventional adders. And also the implementation gives low power results with better performance. Using the available VLSI design techniques and emerging concepts the high speed low power high accurate (HS-LP-HA) Adder is proposed. The proposed HS-LP-HA adder is capable to give near accurate value along with much low power consumption when compared with conventional adder. Hence also improved power delay product. The proposed HS-LP-HA adder finds its applications in signal processing for communications, control of systems, biomedical signal processing and seismic data processing in all which the minute percentage of error is tolerable.

Index Terms—HS-LP-HA adder, speed, low power, accuracy, signal processing, percentage of error.

Muddapu Parvathi is with the Electronics and Communication Engineering Department in Malla Reddy Institute of Technology and Science, Secunderabad, Andhra Pradesh, India, (e-mail: bendalamieee@ gmail.com).
N. Vasantha is with Information Technology Department in Vasavi College of Engineering, Andhra Pradesh, India.
K. Satya Prasad is with the Electronics and Communication Engineering Department, JNTUK, Kakinada, Andhra Pradesh, India.

Cite:Muddapu Parvathi, N. Vasantha, and K. Satya Prasad, "Design of High Speed -Low Power-High Accurate (HS-LP-HA) Adder," International Journal of Computer and Communication Engineering vol. 2, no. 5, pp. 547-550, 2013.