Volume 1 Number 3 (Sep. 2012)
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IJCCE 2012 Vol.1(3): 183-186 ISSN: 2010-3743
DOI: 10.7763/IJCCE.2012.V1.48

Implementation of FPGA-Based Logic Blocks for High Speed Signal Processing System

Cao Bin, Chong Ming Ying, Kyaw Swa Maung, Lai Yoon Fei, Manoj Kumar Dey, and Sandeep Dattaprasad

Abstract—Processing digital signals acquired from high-speed Analog Front Ends (AFE) is of interest in many consumer electronics and PC end applications. This paper presents a modular and structured architecture for processing high speed signals using Field Programmable Gate Arrays(FPGA). In particular it describes the various programmable elements necessary and challenges involved in building such a signal processing system. The approach described here is using Altera's Stratix III and Cyclone II FPGAs. The development was performed using Altera's Quartus 9.1 software environment.

Index Terms—Digital signals, ADC, high speed, field programmable gate array.

Chong Ming Ying, Kyaw Swa Maung, Lai Yoon Fei, Manoj KumarDey, and Sandeep Dattaprasad are with Seagate Techonology, EAO,Advanced Development Engineering, 7000, Ang Mo Kio Ave 5, Singapore569877(e-mail: sandeep.dattaprasad@gmail.com).
Cao Bin is with Institute for Infocomm Research, Embedded Systems Department, Singapore 138632

Cite: Cao Bin, Chong Ming Ying, Kyaw Swa Maung, Lai Yoon Fei, Manoj Kumar Dey, and Sandeep Dattaprasad, "Implementation of FPGA-Based Logic Blocks for High Speed Signal Processing System," International Journal of Computer and Communication Engineering vol. 1, no. 3, pp. 183-186 , 2012.

General Information

ISSN: 2010-3743
Frequency: Quarterly
Editor-in-Chief: Dr. Maode Ma
Abstracting/ Indexing: EI (INSPEC, IET), Google Scholar, Crossref, Engineering & Technology Digital Library, ProQuest, and Electronic Journals Library
E-mail: ijcce@iap.org
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